1. Field of the Invention
The present invention relates to general purpose digital data processing systems, and more particularly to such systems that employ second level caches accessed by a plurality of users over data lines.
2. Description of the Prior Art
In modern high performance data processing systems, significant performance enhancements can be achieved by using the concept of parallelism. Parallelism allows multiple things to occur simultaneously. This may reduce the effects of performance inhibitors such as queuing times that are typically associated with shared resources. Parallelism, however, often requires dedicated interfaces, and thus results in an increase in the number of I/O signals required within the system.
As integrated circuit technology advances, more and more logic can be housed within a single chip. Having more logic within a single chip can result in interface problems if the chip does not have enough I/O pins to provide for all of the input and output signals that are required. In a growing number of cases, there are too few pins to provide dedicated interfaces for all of the desired signals.
Multiprocessor systems that have an instruction processor and a storage controller typically have a function/address interface extending therebetween. In some industry standard systems, the instruction processor interfaces to the storage controller via a dedicated function/address bus, which is a highly parallel connection. In this configuration, the instruction processor may provide the entire address to the storage controller at the beginning of each memory access. This may allow the memory access to be completed in the minimum amount time, at least relative to the shared bus approach, but is typically a relatively expensive solution in terms of I/O pins and interconnect traces.
To overcome these limitations, some systems utilize a serial function/address bus, which is a highly serialized connection. Because the function/address bus is highly serialized, it provides a low cost interface, at least in terms of the number of I/O pins and interconnect, but typically does not provide high performance. Further, as more instruction processors are added to the multiprocessor system, there is typically more contention for the bus and the overall system performance may decrease.
It has been recognized that the optimum design goal may be to maximize the parallelism where it has the most effect on performance, and reduce the parallelism where it has the least affect performance. The result may reduce the number of I/O pins while still providing the desired performance. Thus, it would be desirable to achieve a function/address interface that has the same performance as the fully parallel designs, but with substantially less interconnect.